FPGA prototyping by Verilog examples : (Registro nro. 17995)
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Campo de control de longitud fija | 18123cam a2200253 a 4500 |
001 - NÚMERO DE CONTROL | |
Campo de control | 15153392 |
005 - FECHA Y HORA DE LA ÚLTIMA TRANSACCIÓN | |
Campo de control | 20151209125649.0 |
007 - CAMPO FIJO DE DESCRIPCIÓN FÍSICA | |
DESCRIPCIÓN FÍSICA | ta |
008 - CAMPO FIJO DE DESCRIPCIÓN FIJA--INFORMACIÓN GENERAL | |
Campo de control de longitud fija | 080124s2008 njua b 001 0 eng |
020 ## - ISBN (INTERNATIONAL STANDARD BOOK NUMBER) | |
ISBN | 9780470185322 |
040 ## - FUENTE DE CATALOGACIÓN | |
Agencia de catalogación original | DLC |
Agencia que realiza la transcripción | DLC |
Agencia que realiza la modificación | DLC |
082 00 - NÚMERO DE LA CLASIFICACIÓN DECIMAL DEWEY | |
Número de clasificación Decimal | 621.395 |
Número de edición DEWEY | 22 |
Número de documento (Cutter) | C559f |
100 1# - ENCABEZAMIENTO PRINCIPAL--NOMBRE PERSONAL | |
Nombre de persona | Chu, Pong P., |
Fechas asociadas con el nombre | 1959- |
9 (RLIN) | 26912 |
245 10 - TÍTULO PROPIAMENTE DICHO | |
Título | FPGA prototyping by Verilog examples : |
Parte restante del título | Xilinx Spartan -3 version / |
Mención de responsabilidad, etc. | Pong P. Chu. |
260 ## - PUBLICACIÓN, DISTRIBUCIÓN, ETC (PIE DE IMPRENTA) | |
Lugar de publicación, distribución, etc. | Hoboken, NJ (USA) : |
Nombre del editor, distribuidor, etc. | John Wiley & Sons, |
Fecha de publicación, distribución, etc. | c2008. |
300 ## - DESCRIPCIÓN FÍSICA | |
Extensión | xxvii, 488 p. : |
Otros detalles físicos | il. ; |
Dimensiones | 26 cm. |
504 ## - NOTA DE BIBLIOGRAFÍA, ETC. | |
Bibliografía, etc. | Incluye bibliografía e indices |
505 ## - NOTA DE CONTENIDO FORMATEADA | |
Nota de contenido con formato preestablecido | Acknowledgments. <br/>PART I. BASIC DIGITAL CIRCUITS. <br/>1. Gate-level combinational circuit. <br/>1.1 Introduction. <br/>1.2 General description. <br/>1.3 Basic lexical elements and data types. <br/>1.3.1 Lexical elements. <br/>1.4 Data types. <br/>1.4.1 Four-value system. <br/>1.4.2 Data type groups. <br/>1.4.3 Number representation. <br/>1.4.4 Operators. <br/>1.5 Program skeleton. <br/>1.5.1 Port declaration. <br/>1.5.2 Program body. <br/>1.5.3 Signal declaration. <br/>1.5.4 Another example. <br/>1.6 Structural description. <br/>1.7 Testbench. <br/>1.8 Bibliographic notes. <br/>1.9 Suggested experiments. <br/>1.9.1 Code for gate-level greater-than circuit. <br/>1.9.2 Code for gate-level binary decoder. <br/>2. Overview of FPGA and EDA software. <br/>2.1 Introduction. <br/>2.2 FPGA. <br/>2.2.1 Overview of a general FPGA device. <br/>2.2.2 Overview of the Xilinx Spartan-3 devices. <br/>2.3 Overview of the Digilent S3 board. <br/>2.4 Development flow. <br/>2.5 Overview of the Xilinx ISE project navigator. <br/>2.6 Short tutorial on ISE project navigator. <br/>2.6.1 Create the design project and HDL codes. <br/>2.6.2 Create a testbench and perform the RTL simulation. <br/>2.6.3 Add a constraint file and synthesize and implement the code. <br/>2.6.4 Generate and download the configuration file to an FPGA device. <br/>2.7 Short tutorial on the ModelSim HDL simulator. <br/>2.8 Bibliographic notes. <br/>2.9 Suggested experiments. <br/>2.9.1 Gate-level greater-than circuit. <br/>2.9.2 Gate-level binary decoder. <br/>3. RT-level combinational circuit. <br/>3.1 Introduction. <br/>3.2 Operators. <br/>3.2.1 Arithmetic operators. <br/>3.2.2 Shift operators. <br/>3.2.3 Relational and equality operators. <br/>3.2.4 Bitwise, reduction, and logical operators. <br/>3.2.5 Concatenation and replication operators. <br/>3.2.6 Conditional operators. <br/>3.2.7 Operator precedence. <br/>3.2.8 Expression bit-length adjustment. <br/>3.2.9 Synthesis of z and x values. <br/>3.3 Always block for combinational circuit. <br/>3.3.1 Basic syntax and behavior. <br/>3.3.2 Procedural assignment. <br/>3.3.3 Variable data types. <br/>3.3.4 Simple examples. <br/>3.4 If statement. <br/>3.4.1 Syntax. <br/>3.4.2 Examples. <br/>3.5 Case statement. <br/>3.5.1 Syntax. <br/>3.5.2 Examples. <br/>3.5.3 The casez and casex statements. <br/>3.5.4 The full case and parallel case. <br/>3.6 Routing structure of conditional control constructs. <br/>3.6.1 Priority routing network. <br/>3.6.2 Multiplexing network. <br/>3.7 General coding guidelines for always block 60. <br/>3.7.1 Common errors in combinational circuit codes 60. <br/>3.7.2 Guidelines. <br/>3.8 Parameter and constant. <br/>3.8.1 Constant. <br/>3.8.2 Parameter. <br/>3.8.3 Use of parameter in Verilog-1995. <br/>3.9 Design examples. <br/>3.9.1 Hexadecimal digit to seven-segment LED decoder. <br/>3.9.2 Sign-magnitude adder. <br/>3.9.3 Barrel shifter. <br/>3.9.4 Simplified floating-point adder. <br/>3.10 Bibliographic notes. <br/>3.11 Suggested experiments. <br/>3.11.1 Multi-function barrel shifter. <br/>3.11.2 Dual-priority encoder. <br/>3.11.3 BCD incrementor. <br/>3.11.4 Floating-point greater-than circuit. <br/>3.11.5 Floating-point and signed integer conversion circuit. <br/>3.11.6 Enhanced floating-point adder. <br/>4. Regular Sequential Circuit. <br/>4.1 Introduction. <br/>4.1.1 D FF and register. <br/>4.1.2 Synchronous system. <br/>4.1.3 Code development. <br/>4.2 HDL code of the FF and register. <br/>4.2.1 D FF. <br/>4.2.2 Register. <br/>4.2.3 Register file. <br/>4.2.4 Storage components in a Spartan-3 deviceXilinx specific. <br/>4.3 Simple design examples. <br/>4.3.1 Shift register. <br/>4.3.2 Binary counter and variant. <br/>4.4 Testbench for sequential circuits. <br/>4.5 Case study. <br/>4.5.1 LED time-multiplexing circuit. <br/>4.5.2 Stopwatch 10. <br/>4.5.3 FIFO buffer 110. <br/>4.6 Bibliographic notes. <br/>4.7 Suggested experiments. <br/>4.7.1 Programmable square wave generator. <br/>4.7.2 PWM and LED dimmer. <br/>4.7.3 Rotating square circuit. <br/>4.7.4 Heartbeat circuit. <br/>4.7.5 Rotating LED banner circuit. <br/>4.7.6 Enhanced stopwatch. <br/>4.7.7 Stack. <br/>5. FSM. <br/>5.1 Introduction. <br/>5.1.1 Mealy and Moore outputs. <br/>5.1.2 FSM representation. <br/>5.2 FSM code development. <br/>5.3 Design examples. <br/>5.3.1 Rising-edge detector. <br/>5.3.2 Debouncing circuit. <br/>5.3.3 Testing circuit. <br/>5.4 Bibliographic notes. <br/>5.5 Suggested experiments. <br/>5.5.1 Dual-edge detector. <br/>5.5.2 Alternative debouncing circuit. <br/>5.5.3 Parking lot occupancy counter. <br/>6. FSMD. <br/>6.1 Introduction. <br/>6.1.1 Single RT operation. <br/>6.1.2 ASMD chart. <br/>6.1.3 Decision box with a register. <br/>6.2 Code development of an FSMD. <br/>6.2.1 Debouncing circuit based on RT methodology. <br/>6.2.2 Code with explicit data path components. <br/>6.2.3 Code with implicit data path components. <br/>6.2.4 Comparison. <br/>6.2.5 Testing circuit. <br/>6.3 Design examples. <br/>6.3.1 Fibonacci number circuit. <br/>6.3.2 Division circuit. <br/>6.3.3 Binary-to-BCD conversion circuit. <br/>6.3.4 Period counter. <br/>6.3.5 Accurate low-frequency counter. <br/>6.4 Bibliographic notes. <br/>6.5 Suggested experiments. <br/>6.5.1 Alternative debouncing circuit. <br/>6.5.2 BCD-to-binary conversion circuit. <br/>6.5.3 Fibonacci circuit with BCD I/O: design approach. <br/>6.5.4 Fibonacci circuit with BCD I/O: design approach. <br/>6.5.5 Auto-scaled low-frequency counter. <br/>6.5.6 Reaction timer. <br/>6.5.7 Babbage difference engine emulation circuit. <br/>7. Selected Topics of Verilog. <br/>7.1 Blocking versus nonblocking assignment. <br/>7.1.1 Overview. <br/>7.1.2 Combinational circuit. <br/>7.1.3 Memory element. <br/>7.1.4 Sequential circuit with mixed blocking and nonblocking. <br/>assignments. <br/>7.2 Alternative coding style for sequential circuit. <br/>7.2.1 Binary counter. <br/>7.2.2 FSM. <br/>7.2.3 FSMD. <br/>7.2.4 Summary. <br/>7.3 Use of the signed data type. <br/>7.3.1 Overview. <br/>7.3.2 Signed number in Verilog-1995. <br/>7.3.3 Signed number in Verilog-2001. <br/>7.4 Use of function in synthesis. <br/>7.4.1 Overview. <br/>7.4.2 Examples. <br/>7.5 Additional constructs for testbench development. <br/>7.5.1 Always block and initial block. <br/>7.5.2 Procedural statements. <br/>7.5.3 Timing control. <br/>7.5.4 Delay control. <br/>7.5.5 Event control. <br/>7.5.6 Wait statement. <br/>7.5.7 Timescale directive. <br/>7.5.8 System functions and tasks. <br/>7.5.9 User defined functions and tasks. <br/>7.5.10 Example of a comprehensive testbench. <br/>7.6 Bibliographic notes. <br/>7.7 Suggested experiments. <br/>7.7.1 Shift register with blocking and nonblocking assignments. <br/>7.7.2 Alternative coding style for BCD counter. <br/>7.7.3 Alternative coding style for FIFO buffer. <br/>7.7.4 Alternative coding style for Fibonacci circuit. <br/>7.7.5 Dual-mode comparator. <br/>7.7.6 Enhanced binary counter monitor. <br/>7.7.7 Testbench for FIFO buffer. <br/>PART II. I/O MODULES. <br/>8. UART. <br/>8.1 Introduction. <br/>8.2 UART receiving subsystem. <br/>8.2.1 Oversampling procedure. <br/>8.2.2 Baud rate generator. <br/>8.2.3 UART receiver. <br/>8.2.4 Interface circuit. <br/>8.3 UART transmitting subsystem. <br/>8.4 Overall UART system. <br/>8.4.1 Complete UART core. <br/>8.4.2 UART verification configuration. <br/>8.5 Customizing a UART. <br/>8.6 Bibliographic notes. <br/>8.7 Suggested experiments. <br/>8.7.1 Full-featured UART. <br/>8.7.2 UART with an automatic baud rate detection circuit. <br/>8.7.3 UART with an automatic baud rate and parity detection circuit. <br/>8.7.4 UART-controlled stopwatch. <br/>8.7.5 UART-controlled rotating LED banner. <br/>9. PS2 Keyboard. <br/>9.1 Introduction. <br/>9.2 PS2 receiving subsystem. <br/>9.2.1 Physical interface of a PS2 port. <br/>9.2.2 Device-to-host communication protocol. <br/>9.2.3 Design and code. <br/>9.3 PS2 keyboard scan code. <br/>9.3.1 Overview of the scan code. <br/>9.3.2 Scan code monitor circuit. <br/>9.4 PS2 keyboard interface circuit. <br/>9.4.1 Basic design and HDL code. <br/>9.4.2 Verification circuit. <br/>9.5 Bibliographic notes. <br/>9.6 Suggested experiments. <br/>9.6.1 Alternative keyboard interface I. <br/>9.6.2 Alternative keyboard interface II. <br/>9.6.3 PS2 receiving subsystem with watchdog timer. <br/>9.6.4 Keyboard-controlled stopwatch. <br/>9.6.5 Keyboard-controlled rotating LED banner. <br/>10. PS2 Mouse. <br/>10.1 Introduction. <br/>10.2 PS2 mouse protocol. <br/>10.2.1 Basic operation. <br/>10.2.2 Basic initialization procedure. <br/>10.3 PS2 transmitting subsystem. <br/>10.3.1 Host-to-PS2-device communication protocol. <br/>10.3.2 Design and code. <br/>10.4 Bidirectional PS2 interface. <br/>10.4.1 Basic design and code. <br/>10.4.2 Verification circuit. <br/>10.5 PS2 mouse interface. <br/>10.5.1 Basic design. <br/>10.5.2 Testing circuit. <br/>10.6 Bibliographic notes. <br/>10.7 Suggested experiments. <br/>10.7.1 Keyboard control circuit. <br/>10.7.2 Enhanced mouse interface. <br/>10.7.3 Mouse-controlled seven-segment LED display. <br/>11. External SRAM. <br/>11.1 Introduction. <br/>11.2 Specification of the IS61LV25616AL SRAM. <br/>11.2.1 Block diagram and I/O signals. <br/>11.2.2 Timing parameters. <br/>11.3 Basic memory controller. <br/>11.3.1 Block diagram. <br/>11.3.2 Timing requirement. <br/>11.3.3 Register file versus SRAM. <br/>11.4 A safe design. <br/>11.4.1 ASMD chart. <br/>11.4.2 Timing analysis. <br/>11.4.3 HDL implementation. <br/>11.4.4 Basic testing circuit. <br/>11.4.5 Comprehensive SRAM testing circuit. <br/>11.5 More aggressive design 288. <br/>11.5.1 Timing issues. <br/>11.5.2 Alternative design I. <br/>11.5.3 Alternative design II. <br/>11.5.4 Alternative design III. <br/>11.5.5 Advanced FPGA featuresXilinx specific. <br/>11.6 Bibliographic notes. <br/>11.7 Suggested experiments. <br/>11.7.1 Memory with a 512K-by-16 configuration. <br/>11.7.2 Memory with a 1M-by-8 configuration. <br/>11.7.3 Memory with an 8M-by-1 configuration. <br/>11.7.4 Expanded memory testing circuit. <br/>11.7.5 Memory controller and testing circuit for alternative design I. <br/>11.7.6 Memory controller and testing circuit for alternative design II. <br/>11.7.7 Memory controller and testing circuit for alternative design III. <br/>11.7.8 Memory controller with DCM. <br/>11.7.9 High-performance memory controller. <br/>12. Xilinx Spartan-3 Specific Memory. <br/>12.1 Introduction. <br/>12.2 Embedded memory of Spartan-3 device. <br/>12.2.1 Overview. <br/>12.2.2 Comparison. <br/>12.3 Method to incorporate memory modules. <br/>12.3.1 Memory module via HDL component instantiation. <br/>12.3.2 Memory module via Core Generator. <br/>12.3.3 Memory module via HDL inference. <br/>12.4 HDL templates for memory inference. <br/>12.4.1 Single-port RAM. <br/>12.4.2 Dual-port RAM. <br/>12.4.3 ROM. <br/>12.5 Bibliographic notes. <br/>12.6 Suggested experiments. <br/>12.6.1 Block-RAM-based FIFO. <br/>12.6.2 Block-RAM-based stack. <br/>12.6.3 ROM-based sign-magnitude adder. <br/>12.6.4 ROM based sin(x) function. <br/>12.6.5 ROM-based sin(x) and cos(x) functions. <br/>13. VGA controller I: graphic. <br/>13.1 Introduction. <br/>13.1.1 Basic operation of a CRT. <br/>13.1.2 VGA port of the S3 board. <br/>13.1.3 Video controller. <br/>13.2 VGA synchronization. <br/>13.2.1 Horizontal synchronization. <br/>13.2.2 Vertical synchronization. <br/>13.2.3 Timing calculation of VGA synchronization signals. <br/>13.2.4 HDL implementation. <br/>13.2.5 Testing circuit. <br/>13.3 Overview of the pixel generation circuit. <br/>13.4 Graphic generation with an object-mapped scheme. <br/>13.4.1 Rectangular objects 320. <br/>13.4.2 Non-rectangular object. <br/>13.4.3 Animated object. <br/>13.5 Graphic generation with a bit-mapped scheme. <br/>13.5.1 Dual-port RAM implementation. <br/>13.5.2 Single-port RAM implementation. <br/>13.6 Bibliographic notes. <br/>13.7 Suggested experiments. <br/>13.7.1 VGA test pattern generator. <br/>13.7.2 SVGA mode synchronization circuit. <br/>13.7.3 Visible screen adjustment circuit. <br/>13.7.4 Ball-in-a-box circuit. <br/>13.7.5 Two-balls-in-a-box circuit. <br/>13.7.6 Two-player pong game. <br/>13.7.7 Breakout game. <br/>13.7.8 Full-screen dot trace. <br/>13.7.9 Mouse pointer circuit. <br/>13.7.10 Small-screen mouse scribble circuit. <br/>13.7.11 Full-screen mouse scribble circuit. <br/>14. VGA controller II: text. <br/>14.1 Introduction. <br/>14.2 Text generation. <br/>14.2.1 Character as a tile. <br/>14.2.2 Font ROM. <br/>14.2.3 Basic text generation circuit. <br/>14.2.4 Font display circuit. <br/>14.2.5 Font scaling. <br/>14.3 Full-screen text display. <br/>14.4 The complete pong game. <br/>14.4.1 Text subsystem. <br/>14.4.2 Modified graphic subsystem. <br/>14.4.3 Auxiliary counters. <br/>14.4.4 Top-level system. <br/>14.5 Bibliographic notes. <br/>14.6 Suggested experiments. <br/>14.6.1 Rotating banner. <br/>14.6.2 Underline for the cursor. <br/>14.6.3 Dual-mode text display. <br/>14.6.4 Keyboard text entry. <br/>14.6.5 UART terminal. <br/>14.6.6 Square wave display. <br/>14.6.7 Simple four-trace logic analyzer. <br/>14.6.8 Complete two-player pong game. <br/>14.6.9 Complete breakout game. <br/>PART III. PICOBLAZE MICROCONTROLLERXILINX SPECIFIC. <br/>15. PicoBlaze Overview. <br/>15.1 Introduction. <br/>15.2 Customized hardware and customized software. <br/>15.2.1 From special-purpose FSMD to general-purpose microcontroller. <br/>15.2.2 Application of microcontroller. <br/>15.3 Overview of PicoBlaze. <br/>15.3.1 Basic organization. <br/>15.3.2 Top-level HDL modules. <br/>15.4 Development flow. <br/>15.5 Instruction set. <br/>15.5.1 Programming model. <br/>15.5.2 Instruction format. <br/>15.5.3 Logical instructions. <br/>15.5.4 Arithmetic instructions. <br/>15.5.5 Compare and test instructions. <br/>15.5.6 Shift and rotate instructions. <br/>15.5.7 Data movement instructions. <br/>15.5.8 Program flow control instructions. <br/>15.5.9 Interrupt related instructions. <br/>15.6 Assembler directives. <br/>15.6.1 The KCPSM3 directives. <br/>15.6.2 The PBlazeIDE directives. <br/>15.7 Bibliographic notes. <br/>16. PicoBlaze Assembly Code Development. <br/>16.1 Introduction. <br/>16.2 Useful code segments. <br/>16.2.1 KCPSM3 conventions. <br/>16.2.2 Bit manipulation. <br/>16.2.3 Multiple-byte manipulation. <br/>16.2.4 Control structure. <br/>16.3 Subroutine development. <br/>16.4 Program development. <br/>16.4.1 Demonstration example. <br/>16.4.2 Program documentation. <br/>16.5 Processing of the assembly code. <br/>16.5.1 Compiling with KCSPM3. <br/>16.5.2 Simulation by PBlazeIDE. <br/>16.5.3 Reloading code via the JTAG port. <br/>16.5.4 Compiling by PBlazeIDE. <br/>16.6 Syntheses with PicoBlaze. <br/>16.7 Bibliographic notes. <br/>16.8 Suggested experiments. <br/>16.8.1 Signed multiplication. <br/>16.8.2 Multi-byte multiplication. <br/>16.8.3 Barrel shift function. <br/>16.8.4 Reverse function. <br/>16.8.5 Binary-to-BCD conversion. <br/>16.8.6 BCD-to-binary conversion. <br/>16.8.7 Heartbeat circuit. <br/>16.8.8 Rotating LED circuit. <br/>16.8.9 Discrete LED dimmer. <br/>17. PicoBlaze I/O Interface. <br/>17.1 Introduction. <br/>17.2 Output port. <br/>17.2.1 Output instruction and timing. <br/>17.2.2 Output interface. <br/>17.3 Input port. <br/>17.3.1 Input instruction and timing. <br/>17.3.2 Input interface. <br/>17.4 Square program with a switch and seven-segment LED display interface. <br/>17.4.1 Output interface. <br/>17.4.2 Input interface. <br/>17.4.3 Assembly code development. <br/>17.4.4 HDL code development. <br/>17.5 Square program with a combinational multiplier and UART console. <br/>17.5.1 Multiplier interface. <br/>17.5.2 UART interface. <br/>17.5.3 Assembly code development. <br/>17.5.4 HDL code development. <br/>17.6 Bibliographic notes. <br/>17.7 Suggested experiments. <br/>17.7.1 Low-frequency counter I. <br/>17.7.2 Low-frequency counter II. <br/>17.7.3 Auto-scaled low-frequency counter. <br/>17.7.4 Basic reaction timer with a software timer. <br/>17.7.5 Basic reaction timer with a hardware timer. <br/>17.7.6 Enhanced reaction timer 450. <br/>17.7.7 Small-screen mouse scribble circuit 450. <br/>17.7.8 Full-screen mouse scribble circuit 450. <br/>17.7.9 Enhanced rotating banner 450. <br/>17.7.10 Pong game 450. <br/>17.7.11 Text editor 450. <br/>18. PicoBlaze Interrupt Interface. <br/>18.1 Introduction. <br/>18.2 Interrupt handling in PicoBlaze. <br/>18.2.1 Software processing. <br/>18.2.2 Timing. <br/>18.3 External interface. <br/>18.3.1 Single interrupt request. <br/>18.3.2 Multiple interrupt requests. <br/>18.4 Software development considerations. <br/>18.4.1 Interrupt as an alternative scheduling scheme. <br/>18.4.2 Development of an interrupt service routine. <br/>18.5 Design example. <br/>18.5.1 Interrupt interface. <br/>18.5.2 Interrupt service routine development. <br/>18.5.3 Assembly code development. <br/>18.5.4 HDL code development. <br/>18.6 Bibliographic notes. <br/>18.7 Suggested experiments. <br/>18.7.1 Alternative timer interrupt service routine. <br/>18.7.2 Programmable timer. <br/>18.7.3 Set-button interrupt service routine. <br/>18.7.4 Interrupt interface with two requests. <br/>18.7.5 Four-request interrupt controller. <br/>Appendix A: Sample Verilog templates. <br/>A.1 Numbers and operators. <br/>A.1.1 Sized and unsized numbers. <br/>A.1.2 Operators. <br/>A.2 General Verilog constructs. <br/>A.2.1 Overall code structure. <br/>A.2.2 Component instantiation. <br/>A.3 Routing with conditional operator and if and case statements. <br/>A.3.1 Conditional operator and if statement. <br/>A.3.2 Case statement. <br/>A.4 Combinational circuit using always block. <br/>A.4.1 Always block without default output assignment. <br/>A.4.2 Always block with default output assignment. <br/>A.5 Memory Components. <br/>A.5.1 Register template. <br/>A.5.2 Register file. <br/>A.6 Regular sequential circuits. <br/>A.7 FSM. <br/>A.8 FSMD. <br/>A.9 S3 board constraint file (s3.ucf) 4. <br/>References. <br/>Topic Index. |
520 ## - RESUMEN, ETC. | |
Nota de sumario, etc. | FPGA Prototyping Using Verilog Examples le proporcionará una introducción práctica a la síntesis Verilog y programación FPGA a través de un "aprender haciendo". Siguiendo las claras y fáciles de entender plantillas para el desarrollo de código y los numerosos ejemplos prácticos, se puede desarrollar rápidamente y simular un circuito digital sofisticada, realizarlo en un dispositivo de creación de prototipos, y verificar el funcionamiento de su implementación física. Este texto introductorio que le proporcionará una base sólida, infundir confianza con ejemplos rigurosos para sistemas complejos y prepararse para las tareas de desarrollo futuro. |
650 #0 - ASIENTO SECUNDARIO DE MATERIA--TÉRMINO DE MATERIA | |
Nombre de materia o nombre geográfico como elemento de entrada | INGENIERÍA DE PROTOTIPOS |
9 (RLIN) | 622 |
650 #0 - ASIENTO SECUNDARIO DE MATERIA--TÉRMINO DE MATERIA | |
Nombre de materia o nombre geográfico como elemento de entrada | VERILOG (LENGUAJE DE DESCRIPCIÓN DE HARDWARE) |
9 (RLIN) | 26913 |
856 41 - ACCESO ELECTRÓNICO | |
Materiales específicos | Table of contents only |
Identificador uniforme del recurso URI | <a href="http://www.loc.gov/catdir/enhancements/fy0810/2008003732-t.html">http://www.loc.gov/catdir/enhancements/fy0810/2008003732-t.html</a> |
Texto del enlace | Tabla de Contenido |
942 ## - ELEMENTOS KOHA | |
Fuente de clasificación o esquema de ordenación en estanterías | |
Koha tipo de item | LIBRO - MATERIAL GENERAL |
Disponibilidad | Mostrar en OPAC | Fuente de clasificación o esquema | Tipo de Descarte | Estado | Código de colección | Localización permanente | Localización actual | Localización en estanterías | Fecha adquisición | Proveedor | Forma de Adq | Precio normal de compra | Datos del ítem (Volumen, Tomo) | Número de Inventario | Préstamos totales | Renovaciones totales | Signatura completa | Código de barras | Fecha última consulta | Fecha último préstamo | Número de ejemplar | Coste, precio de reemplazo | Propiedades de Préstamo KOHA | Programa Académico |
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Préstamo Normal | Colección General | Biblioteca Jorge Álvarez Lleras | Biblioteca Jorge Álvarez Lleras | Fondo general | 2015-12-09 | BuscaLibre-900566941-OC21315 | Compra | 293200.00 | Ej. 1 | BIB0001665 | 10 | 9 | 621.395 C559f | 024746 | 2024-02-27 | 2024-02-16 | 1 | 293200.00 | LIBRO - MATERIAL GENERAL | Ingenieria Sistemas |