High-Level Verification [electronic resource]: Methods and Tools for Verification of System-Level Designs / by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta.
Tipo de material: TextoDescripción: XIII, 167p. 31 illus. online resourceISBN: 9781441993595 99781441993595Tema(s): Engineering | Engineering | COMPUTER, AIDED ENGINEERING (CAD, CAE) AND DESIGN | COMPUTER AIDED DESIGN | CIRCUITS AND SYSTEMS | SYSTEMS ENGINEERINGClasificación CDD: 621.3815 Recursos en línea: ir a documentoTipo de ítem | Ubicación actual | Colección | Signatura | Info Vol | Copia número | Estado | Fecha de vencimiento | Código de barras | Reserva de ítems |
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DOCUMENTOS DIGITALES | Biblioteca Jorge Álvarez Lleras | Digital | 621.3815 223 (Navegar estantería) | Ej. 1 | 1 | Disponible | D000417 |
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621.3815 223 Nano-Electronic Devices | 621.3815 223 CMOS Integrated Switching Power Converters | 621.3815 223 Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs | 621.3815 223 High-Level Verification | 621.3815 223 CMOS High Efficiency On-chip Power Management | 621.3815 223 Hardware /Software Architectures for Low-Power Embedded Multimedia Systems | 621.3815 223 VCO-Based Quantizers Using Frequency-to-Digital and Time-to-Digital Converters |
Introduction -- Related Work -- Background -- Execution-based Model Checking for High-Level Designs -- Efficient Symbolic Analysis for Concurrent Programs -- Translation Validation of High-Level Synthesis -- Parameterized Program Equivalence Checking -- Conclusions and Future Work.
This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence the topic area is also referred to as system level verification. Since such descriptions can also capture software, especially device drivers or other embedded software, this book will be of interest to both hardware and software designers. The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification; Uses a combination of formal techniques to do scalable verification of system designs completely automatically; Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL; Written by researchers working in mainstream hardware and software design and includes results from both academia and industry.
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