Reconfigurable Computing [electronic resource]: From FPGAs to Hardware/Software Codesign / edited by Joao M. P. Cardoso, Michael Hubner.
Tipo de material: TextoDescripción: XV, 296p. 107 illus. online resourceISBN: 9781461400615 99781461400615Tema(s): Engineering | Engineering | COMPUTER, AIDED ENGINEERING (CAD, CAE) AND DESIGN | COMPUTER AIDED DESIGN | CIRCUITS AND SYSTEMS | SYSTEMS ENGINEERINGClasificación CDD: 621.3815 Recursos en línea: ir a documentoTipo de ítem | Ubicación actual | Colección | Signatura | Info Vol | Copia número | Estado | Fecha de vencimiento | Código de barras | Reserva de ítems |
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DOCUMENTOS DIGITALES | Biblioteca Jorge Álvarez Lleras | Digital | 621.3815 223 (Navegar estantería) | Ej. 1 | 1 | Disponible | D000643 |
Navegando Biblioteca Jorge Álvarez Lleras Estantes, Código de colección: Digital Cerrar el navegador de estanterías
621.3815 223 Formal Development of a Network-Centric RTOS | 621.3815 223 Programming Many-Core Chips | 621.3815 223 High-Speed Optical Receivers with Integrated Photodiode in Nanoscale CMOS | 621.3815 223 Reconfigurable Computing | 621.3815 223 Minimizing Spurious Tones in Digital Delta-Sigma Modulators | 621.3815 223 Automatic Gain Control | 621.3815 223 Oversampling A /D Converters with Improved Signal Transfer Functions |
Introduction -- The Relevance of Reconfigurable Computing -- HiPEAC: Upcoming Challenges in Reconfigurable Computing -- MORPHEUS: Exploitation of Reconfiguration for Increased Run-time Flexibility and Self-adaptive Capabilities in Future SoCs -- hArtes: Holistic Approach to Reconfigurable Real-time Embedded Systems -- Smart Chips for Smart Surroundings -- AETHER: Self-adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies -- ANDRES: Analysis and Design of Run-time Reconfigurable, Heterogeneous Systems -- CRISP: Cutting Edge Reconfigurable ICs for Stream Processing -- ERA: Embedded Reconfigurable Architectures -- REFLECT: Rendering FGGAs to Multi-core Embedded Computing -- Conclusion.
As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic. Focuses on both hardware and software systems Treats FPGAs as computing vehicles rather than glue-logic or ASIC substitutes Assembles broad set of models for exploiting FPGA parallelism Demonstrates how to use and manage reconfiguration Provides broad set of case studies demonstrating how to use FPGAs in novel and efficient ways.
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