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Time-interleaved Analog-to-Digital Converters [electronic resource] / by Simon Louwsma, Ed Tuijl, Bram Nauta.

By: Louwsma, Simon [author.].
Contributor(s): Tuijl, Ed | [author.] | Nauta, Bram | [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Analog Circuits and Signal Processing.Description: XVI, 136p. online resource.ISBN: 9789048197163 99789048197163.Subject(s): Engineering | Engineering | CIRCUITS AND SYSTEMS | SYSTEMS ENGINEERINGDDC classification: 621.3815 Online resources: ir a documento Summary: Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
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Item type Current location Collection Call number Vol info Copy number Status Date due Barcode Item holds
DOCUMENTOS DIGITALES DOCUMENTOS DIGITALES Biblioteca Jorge Álvarez Lleras
Digital 621.3815 223 (Browse shelf) Ej. 1 1 Available D000747
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Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.

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