Time-interleaved Analog-to-Digital Converters [electronic resource] / by Simon Louwsma, Ed Tuijl, Bram Nauta.
Tipo de material: TextoSeries Analog Circuits and Signal ProcessingDescripción: XVI, 136p. online resourceISBN: 9789048197163 99789048197163Tema(s): Engineering | Engineering | CIRCUITS AND SYSTEMS | SYSTEMS ENGINEERINGClasificación CDD: 621.3815 Recursos en línea: ir a documento Resumen: Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.Tipo de ítem | Ubicación actual | Colección | Signatura | Info Vol | Copia número | Estado | Fecha de vencimiento | Código de barras | Reserva de ítems |
---|---|---|---|---|---|---|---|---|---|
DOCUMENTOS DIGITALES | Biblioteca Jorge Álvarez Lleras | Digital | 621.3815 223 (Navegar estantería) | Ej. 1 | 1 | Disponible | D000747 |
Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
No hay comentarios en este titulo.