Low-Power High-Resolution Analog to Digital Converters [electronic resource]: Design, Test and Calibration / by Amir Zjajo, José Pineda de Gyvez.
Tipo de material: TextoSeries Analog Circuits and Signal ProcessingDescripción: XX, 250p. 100 illus. in color. online resourceISBN: 9789048197255 99789048197255Tema(s): Engineering | Engineering | COMPUTER, AIDED ENGINEERING (CAD, CAE) AND DESIGN | COMPUTER AIDED DESIGN | ELECTRONICS AND MICROELECTRONICS, INDTRUMENTATION | CIRCUITS AND SYSTEMS | ELECTRONICS | SYSTEMS ENGINEERINGClasificación CDD: 621.381 Recursos en línea: ir a documentoTipo de ítem | Ubicación actual | Colección | Signatura | Info Vol | Copia número | Estado | Fecha de vencimiento | Código de barras | Reserva de ítems |
---|---|---|---|---|---|---|---|---|---|
DOCUMENTOS DIGITALES | Biblioteca Jorge Álvarez Lleras | Digital | 621.381 223 (Navegar estantería) | Ej. 1 | 1 | Disponible | D000501 |
Navegando Biblioteca Jorge Álvarez Lleras Estantes, Código de colección: Digital Cerrar el navegador de estanterías
621.381 223 Strain-Induced Effects in Advanced MOSFETs | 621.381 223 Deterministic Solvers for the Boltzmann Transport Equation | 621.381 223 Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters | 621.381 223 Low-Power High-Resolution Analog to Digital Converters | 621.381 223 Solutions on Embedded Systems | 621.381 223 Electrical Engineering and Applied Computing | 621.381 223 Sensors and Microsystems |
Foreword -- Abbrevations.--Symbols -- 1. Introduction -- 2. Analog to Digital Conversion -- 3. Design of Multi-Step A/D Converters -- 4. Multi-Step A/D Converter Testing -- 5. Multi-Step A/D Converter Debugging -- 6. Conclusions and Recommendations -- Appendix -- References -- Index.-.
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
No hay comentarios en este titulo.