Implementation of the Parallel Redundancy Protocol (PRP) with encryption of frames using the Advanced Encryption Standard (AES) : [Recurso Electrónico] / Marco Andrés Ortiz Niño.

Por: Ortiz Niño, Marco AndrésColaborador(es): Paz, Hernán [director.]Tipo de material: Archivo de ordenadorArchivo de ordenadorEditor: Bogotá (Colombia): Escuela Colombiana de Ingeniería Julio Garavito, 2021Descripción: 136 paginas. gráficosTema(s): REDUNDANCIA ( INGENIERÍA ) | CIFRADO DE DATOS ( COMPUTADORES ) -- SEGURIDAD INFORMÁTICA | TESIS DE GRADOClasificación CDD: 621.382 Recursos en línea: Haga clic para acceso en línea Nota de disertación: Tesis (Magíster en Ingeniería Electrónica) Resumen: As industrial Networks progressively migrate their communications infrastructure to IP and Ethernet set of protocols, threads and vulnerabilities also appear to disrupt operation of infrastructure with serious repercussions. To minimize these, authentication, encryption, integrity and availability must be taken in consideration at every layer of the communication architecture. Security can be achieved by numerous algorithms and set protocols that are continuously tested and implemented to be supported on current links, networks and applications. Their implementations are performed to accomplish high throughput and reduced logic utilization depending on industry or sector requirements. Particularly, this work deals with confidentiality and availability at data link layer where Ethernet resides. Advanced Encryption Standard (AES) with Counter mode (CTR) are used for confidentiality and the Parallel Redundancy Protocol (PRP) for redundancy. These are selected due to their communication orientation, broad operation lifetime expectancy, and their direct relation to secure industrial networks for critical and non-critical infrastructures. Advanced Encryption Standard (AES)- Counter mode (CTR) logic an its Intellectual Property (IP) Cores are created using Very High Speed Integrated Circuit Hardware Description Language (VHDL) within Xilinx Vivado and tested using the Zynq7000 System on Chip (SoC)-Field Programable Gate Array (FPGA) and Kintex 7 FPGA. Parallel Redundancy Protocol (PRP) is implemented on software to govern the protocol algorithm, data encryption operation and packet framing. To test integration between these components, the embedded processor of the Zynq 7000 (ARM) and Microblaze are used. This work presents a non-pipelined AES implementation for confidentiality, its logic utilization, maximum frequency and throughput. Results for AES are also presented in simulation for 128, 192 and 256 bit-length key sizes. At implementation, the 128 bit key is used. For redundancy, on the other hand, the PRP is implemented on software, which creates the header and trailer according to International Electrotechnical Commission (IEC) specification, and, a packet format is proposed to encrypted payloads. Integration results of AES-PRP are seen as packets that were captured in between of the communication devices.
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Tesis (Magíster en Ingeniería Electrónica)

As industrial Networks progressively migrate their communications infrastructure to IP and Ethernet set of protocols, threads and vulnerabilities also appear to disrupt operation of infrastructure with serious repercussions. To minimize these, authentication, encryption, integrity and availability must be taken in consideration at every layer of the communication architecture. Security can be achieved by numerous algorithms and set protocols that are continuously tested and implemented to be supported on current links, networks and applications. Their implementations are performed to accomplish high throughput and reduced logic utilization depending on industry or sector requirements. Particularly, this work deals with confidentiality and availability at data link layer where Ethernet resides. Advanced Encryption Standard (AES) with Counter mode (CTR) are used for confidentiality and the Parallel Redundancy Protocol (PRP) for redundancy. These are selected due to their communication orientation, broad operation lifetime expectancy, and their direct relation to secure industrial networks for critical and non-critical infrastructures. Advanced Encryption Standard (AES)- Counter mode (CTR) logic an its Intellectual Property (IP) Cores are created using Very High Speed Integrated Circuit Hardware Description Language (VHDL) within Xilinx Vivado and tested using the Zynq7000 System on Chip (SoC)-Field Programable Gate Array (FPGA) and Kintex 7 FPGA. Parallel Redundancy Protocol (PRP) is implemented on software to govern the protocol algorithm, data encryption operation and packet framing. To test integration between these components, the embedded processor of the Zynq 7000 (ARM) and Microblaze are used. This work presents a non-pipelined AES implementation for confidentiality, its logic utilization, maximum frequency and throughput. Results for AES are also presented in simulation for 128, 192 and 256 bit-length key sizes. At implementation, the 128 bit key is used. For redundancy, on the other hand, the PRP is implemented on software, which creates the header and trailer according to International Electrotechnical Commission (IEC) specification, and, a packet format is proposed to encrypted payloads. Integration results of AES-PRP are seen as packets that were captured in between of the communication devices.

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