CATÁLOGO EN LÍNEA
Biblioteca JAL

BIBLIOTECA

JORGE ÁLVAREZ LLERAS

On-Chip Interconnect with aelite [electronic resource]: Composable and Predictable Systems / Andreas Hansson.

Por: Colaborador(es): Tipo de material: TextoSeries Embedded Systems | Descripción: X, 210 p. online resourceISBN:
  • 9781441968654 99781441968654
Tema(s): Clasificación CDD:
  • 621.3815 223
Recursos en línea: Resumen: On-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. -Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; "óUses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; -Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); -Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.
Etiquetas de esta biblioteca: No hay etiquetas de esta biblioteca para este título. Ingresar para agregar etiquetas.
Valoración
    Valoración media: 0.0 (0 votos)
Existencias
Imagen de cubierta Tipo de ítem Biblioteca actual Biblioteca de origen Colección Ubicación en estantería Signatura topográfica Materiales especificados Info Vol URL Copia número Estado Notas Fecha de vencimiento Código de barras Reserva de ítems Prioridad de la cola de reserva de ejemplar Reservas para cursos
DOCUMENTOS DIGITALES Biblioteca Jorge Álvarez Lleras Digital 621.3815 223 (Navegar estantería(Abre debajo)) Ej. 1 1 Disponible D000606
Total de reservas: 0

On-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. -Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; "óUses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; -Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); -Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.

No hay comentarios en este titulo.

para colocar un comentario.


Código QR

BIBLIOTECA

JORGE ÁLVAREZ LLERAS
Información de la biblioteca

Horario

Lunes a Viernes:
6:30 am - 7:30 pm

Sábados:
8:00 am - 2:00 pm

Contacto

Teléfono: +57 601 668 3600

biblioteca@escuelaing.edu.co

Ubicación

Biblioteca Central: Bloque B

Biblioteca Satélite: Bloque G