000			03196nam a2200253za04500
001			17122
008			050703s2011 xxu eng d
020			_a9781441975485 99781441975485
082			_a621.3815 _b223
100			_aNavabi, Zainalabedin. _eauthor. _934508
245			_aDigital System Test and Testable Design _h[electronic resource]: _bUsing HDL Models and Architectures / _cby Zainalabedin Navabi.
300			_aXVII, 435p. 100 illus. _bonline resource.
520			_aDigital System Test and Testable Design: Using HDL Models and Architectures by: Zainalabedin Navabi This book is about digital system test and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware _asoftware environment facilitates description of complex test programs and test strategies. Combines design and test Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods Virtual testers (Verilog testbenches) play the role of ATEs for driving scan tests and examining the circuit under test "óVerilog descriptions of scan designs and BIST architectures are available that can be used in actual designs "óPLI test utilities developed in-text are available for download Introductory Video for Verilog basics, software developed in-text, and PLI basics available for download Powerpoint slides available for each chapter
650			_923197 _aMATHEMATICS
650			_934509 _aPOPULAR SCIENCE
650			_933692 _aSCIENCE (GENERAL)
650			_933696 _aMATHEMATICS, GENERAL
650			_933660 _aCIRCUITS AND SYSTEMS.
650			_933673 _aSYSTEMS ENGINEERING
650			_934510 _aPHILOSOPHY
710			_aSpringerLink (Online service) _9111
856			_uhttp://springer.escuelaing.metaproxy.org/book/10.1007/978-1-4419-7548-5 _yir a documento _qURL
942			_2ddc _cCF
999			_c13887 _d13887