000			02007nam a2200277za04500
001			17765
008			050703s2011 ne eng d
020			_a9789048197163 99789048197163
082			_a621.3815 _b223
100			_aLouwsma, Simon. _eauthor. _936033
245			_aTime-interleaved Analog-to-Digital Converters _h[electronic resource] / _cby Simon Louwsma, Ed Tuijl, Bram Nauta.
300			_aXVI, 136p. _bonline resource.
490			_aAnalog Circuits and Signal Processing
520			_aTime-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
650			_aEngineering. _996
650			_aEngineering. _996
650			_933660 _aCIRCUITS AND SYSTEMS.
650			_933673 _aSYSTEMS ENGINEERING
700			_aTuijl, Ed. _936034
700			_eauthor. _936035
700			_aNauta, Bram. _936036
700			_eauthor. _936035
710			_aSpringerLink (Online service) _9111
856			_uhttp://springer.escuelaing.metaproxy.org/book/10.1007/978-90-481-9716-3 _yir a documento _qURL
942			_2ddc _cCF
999			_c14387 _d14387